In a complete system such as a computer, there is generally more than one power supply voltage. Different integrated circuits (ICs), or different chips, in the system may use different supply voltages and a mixed-voltage input/output (I/O) buffer circuit is generally necessary between different chips of the system with different power supply voltages.
In a system including a first circuit on a first chip and a second circuit on a second chip with an I/O buffer circuit coupled therebetween, the buffer circuit may have two operation modes. For the purpose of description, it is assumed that a power supply of the first circuit has a lower voltage level than that of the second circuit and the I/O buffer circuit has the same power supply as that of the first circuit, e.g., the first circuit and the I/O buffer circuit may have a power supply of 1.8V or 3.3V and the second circuit may have a power supply of 3.3V or 5V, respectively. An output mode is then defined as when the buffer receives one or more signals from the first circuit and outputs one or more signals to the second circuit. An input mode is defined as when the buffer receives one or more signals from the second circuit and outputs one or more signals back to the first circuit. In the output mode, the buffer should not be affected by the second circuit, while in the input mode, the buffer should not be affected by the first circuit.
In the output mode when the buffer takes signals from the first circuit and generates certain signals to the second circuit, the buffer operates normally, however, problems may occur when the buffer circuit operates in the input mode. Two problems associated with an I/O buffer in a mixed-voltage system are explained with reference to FIG. 1.
FIG. 1 shows a conventional buffer circuit 100 used in a mixed-voltage system. Buffer circuit 100 on a first chip having a logic circuit 102 and a driver circuit 104 is coupled to a first circuit 106 on the first chip and, through a bonding pad 108, to a second circuit 110 on a second chip. Buffer circuit 100 has a power supply voltage VDD of 1.8V and second circuit 110 has a power supply voltage of 3.3V. Driver circuit 104 includes a PMOS transistor 112 and an NMOS transistor 114, both of which are driven by logic circuit 102. Drain terminals of both PMOS transistor 112 and NMOS transistor 114 are coupled together and further coupled to bonding pad 108. Both a source and a substrate terminal of PMOS transistor 112 are coupled to VDD. There is also a parasitic diode 116 between the drain and substrate of PMOS transistor 112.
A first problem occurs in the input mode when second circuit 110 outputs a logic “1”, e.g., 3.3V, to bonding pad 108. Since PMOS transistor 112 has a drain voltage of 3.3V and a substrate, or n-well, voltage of 1.8V, the drain-substrate p-n junction of PMOS transistor 112 is forward biased, thereby causing a substantial amount of current flowing through diode 116 from bonding pad 108 to VDD.
Furthermore, when bonding pad 108 is at 3.3V, while the gate of PMOS transistor 112 is at either 1.8V or 0V, PMOS transistor 112 is turned on due to the positive bias of its drain terminal with respect to its gate terminal. Therefore, current flows through transistor 112 from bonding pad 108 to the VDD terminal. This means that even in a state when PMOS transistor 112 is supposed to be off, i.e., when the gate is biased at 1.8V, PMOS transistor 112 may still be on and conducting current from bonding pad 108 to the VDD terminal.